The present invention is an architecture for computers which utilizes selective global interconnects between its logic gates and is based on a new class of digital logic. The use of selective global interconnects permits the efficient routing of signals between the logic gates and enables the computer to perform multiple, complex calculations simultaneously. This allows the efficient calculation of an entire set of user instructions, and increases the range of problems and disciplines to which the architecture can be applied.
The new class of digital logic combines semiconductor based logic families (such as those based on GaAs) with digital optic logic in order to obtain the benefits of both types of logic, while overcoming limitations of purely semiconductor based logics. This assists in making the computing architecture commercially viable because it provides a computation capacity/cost ratio which is economically competitive with presently available architectures.
Computing architectures based solely on electronic or semiconductor technologies are well known and have been in use for some time. Optical computer architectures have also received a great deal of attention and are perceived as promising designs for computers. One of the inventors of the present application (Guilfoyle) has previously described in U.S. Pat. No. 4,864,524, entitled "Combinatorial Logic-Based Optical Computing Method and Apparatus", issued Sep. 5, 1989, a computing architecture which utilizes electronic and optical components. The architecture utilizes parallel gate interconnects between two sets of input data gates, and discusses the use of a more general, global interconnect structure.
The replacement of the second set of input data gates by a set of program control data gates was taught by Guilfoyle in copending U.S. patent application Ser. No. 639,284, entitled "General Purpose Optical Computer", filed Jan. 10, 1991. This results in a computer which can implement a greater variety of switching functions or user instructions, and hence is more powerful and versatile. It also provides the capability for a programmable architecture which can be used to implement multiple user instructions in successive passes through the device.
The gate interconnect structure of the computing architecture is a significant issue because it impacts the physical size, calculation capacity, and speed of a computer. Current architectures for optical computers primarily utilize parallel interconnects between their optical logic gates. This simplifies the design and implementation of the apparatus, but results in one of less efficiency, and one which may require pre-conditioning or duplicative processing of inputs in order to generate the full array of potential user instructions.
A selective global interconnect architecture for the optical gates of a computing apparatus in accordance with the present invention is capable of generating an arbitrary instruction set more efficiently because more, if not all, combinations of terms of which the instructions are composed can be produced simultaneously. This increases the computational speed of the computer, reduces the number of calculation specific gate structures required, and favorably impacts the commercial viability of a computer based on the architecture. This is because the computation rate/cost ratio strongly influences the desirability of a particular computer or architecture.
The combination of semiconductor based and digital optical logics provides a commercially viable design and overcomes some of the limitations inherent in semiconductor based architectures. In order to make these benefits clearer, some of the present limitations of GaAs semiconductor technology when used as the basis for a computing architecture will be discussed.
In "An Introduction for GaAs Microprocessor Architecture", in Reduced Instruction Set Computers, William Stallings, editor, IEEE Computer Society Press, 1990, Dr. Walter Helbig of RCA's Advanced Technology Laboratories addresses GaAs semiconductor technology. Dr. Helbig introduces an example implementing the ADD algorithm on the co-processor area of the chip. The article discusses some of the inherent problems in the use of GaAs technology as the basis for a computing architecture. It has been discovered that digital optical logic, when used to complement GaAs, eliminates many of these problems, and can be used to leverage the performance of the GaAs based logic family.
As Dr. Helbig notes, "In the GaAs environment, simple adder designs such as ripple-carry and carry-select are better. The carry-lookahead design is plagued with very large gate fan-ins and fan-outs. Low Fan-in and fan-out of GaAs gates, although not believed to be a permanent characteristic, nevertheless currently introduce constraints not found in silicon. Gate fan-out can generally be increased by using larger transistors, as is done in silicon. However, low gate fan-in is a serious problem, particularly for NAND gates. This is because an increase in the number of inputs to a NAND gates reduces the noise margin, and noise margins are very small in GaAs devices to begin with."
"Because of the limited fan-in of GaAs gates, the ripple-carry approach may be faster for a GaAs VLSI implementation. Even if not the fastest, the ripple-carry approach may still be preferred because of its low layout area requirements. As mentioned earlier, GaAs gates are now often characterized with low fan-in and fan-out capabilities. Therefore, additional gates must be used to implement a carry lookahead adder. Because carry-lookahead is an irregular adder design, it has a large area requirement."
The Fan-In and Fan-Out limitations of GaAs technology restricts the number of input and output channels per logic gate, and hence increases the number of gates required for implementing complex instructions. This impacts the physical size and power consumption requirements of the architecture.
The noise margin problem referred to by Dr. Helbig is a drawback to using GaAs technology because it impacts the signal-to-noise ratio (SNR) and the bit error rate achievable by the architecture (and hence the computational reliability and reproducibility, and the capability of the architecture to discriminate between logic states).
The gate interconnect structure of a GaAs based architecture determines to some extent the type and complexity of algorithms which can be used to implement instruction sets, and as noted can result in inefficiencies and increased layout area requirements. This is a drawback to using GaAs based architectures because it increases the computation time, complexity, and physical size of the architecture, impacting performance and development costs.
In contrast, a digital optical logic family can capitalize on the inherent benefits of optical computing which include high Fan-In and Fan-Out capability, low power consumption, high noise margin, high algorithmic efficiency using "smart" interconnects, and free space leverage of GIBP (gate interconnect bandwidth product).
Other secondary advantages of optical logic include (but are not limited to) zero capacitive loading of signals at a detector, zero cross-talk between signals, zero signal dispersion, and minimal clock skew (a few picoseconds or less in an imaging system). The use of optical logic in conjunction with semiconductor based logic can thus address some of the limitations of the latter while achieving the benefits of the former.